There are many processes in the design of a semiconductor large-scale integrated circuit (LSI) needed to operate in a high frequency as in a CPU and the like. Recently, due to the fineness by the progress of a process technology and the increase of a circuit scale accompanying the fineness, it has become difficult to design the layout of the entire LSI. Therefore, in such a layout design it is common that the entire LSI is divided into a plurality of modules and a design is made in parallel for each module.
In the initial stage of the layout design, the detail of each module is not yet determined. Therefore, usually a floor plan is manually made taking a circuit scale, the rough flow of a signal and the like into consideration in advance and then the rough location and shape of each module are determined. In the floor plan, besides, the location of the external terminal of a module (module terminal) becoming the interface of the module is determined. The module terminal is used for connection of the modules or as the external terminal of a chip.
When a design method for dividing the entire LSI into modules and making their layout designs in parallel is adopted, it becomes preferable to review them in order to optimize the location of the module terminal. As the optimization method, a method for applying optimization to wiring in which there is a big difference between wire lengths calculated on the basis of a determined route and a wire length estimated from a distance between module terminals, again, a method for determining a rough route in advance and putting an actually designed route within the rough route and the like are known.
A high-speed operation and the fineness of a process give a serious influence to the wiring delay of signals. Since there is a coupling capacity being a capacity between wires caused between two parallel wires, it is known that crosstalk noise is caused by the change of signals in one wire causing an electromotive force in another wire. The crosstalk noise causes inconveniences, such as delay increase, a miss-operation and the like. Therefore, recently, even in the initial stage of a layout design, a design taking the occurrence of inconveniences into consideration has been needed.
As countermeasures against crosstalk noise, space between wires is broadened. When a wire is connected to the module terminal, it is common to modify the disposition of the module terminal.
Next, a conventional layout design support apparatus for supporting a layout design by dividing a semiconductor integrated device into a plurality of modules will be explained in detail with reference to a functional configuration illustrated in FIG. 1.
This conventional layout design supporting apparatus inputs a logically designed semiconductor integrated circuit, such as a net list, disassembles the semiconductor integrated circuit into a plurality of modules according to a floor plan and supports the detailed design for determining the disposition of cells and wiring for each module. For this purpose, the conventional layout design supporting apparatus includes a module shape determination unit 11, a rough wiring unit 12, a terminal position adjustment unit 13, a module division unit and a detailed design unit 15.
The module shape determination unit 11 makes a floor plan for determining the shape and disposition of modules dividing a semiconductor integrated circuit according to the instructions of a designer. Each module is a part of the semiconductor integrated circuit and signals determined by a logical design are transmitted/received between the modules. The signals to be transmitted/received are automatically determined accompanying the assignment of functions to the modules. The rough wiring unit 12 determines rough wiring for transmitting/receiving the signals between the modules. The terminal position adjustment unit 13 adjusts (modifies) the position of each module terminal whose disposition range is restricted by the determination of the rough wiring. The module division unit 14 divides the semiconductor integrated circuit into a plurality of modules according to the floor plan.
FIG. 1 illustrates that three pieces of module data D1 are generated by dividing the semiconductor integrated circuit into three modules. Each piece of module data D1 includes a net list for a corresponding module, disposition information indicating the disposition of each module terminal and disposition information indicating the shape and disposition of the module.
The detailed design unit 15 performs a detailed design for determining the disposition of each cell indicated by the data D1 and wiring for each module data D1. Each design result is outputted as module data D2. This data D2 is obtained, for example, by adding disposition information indicating the disposition of each cell, wire information indicating the route of each wire and the like to the module data D1. The wire information of each wire indicates the pins of each cell connected by the wire, a route between pins and the like.
FIG. 2 illustrates an example of module division. In this division example, a semiconductor integrated circuit 30 is divided into four modules 31 through 34. In FIG. 2, the module is described as a “BLOCK”.
The module 32 illustrated in FIG. 2 is one whose disposition and wiring is determined. A hatched rectangle with “CL” attached and a rectangle with “ST” attached indicate a cell and a site being an area in which cells CL are collectively disposed, respectively. A solid line connecting between cells CL existing in different sites indicates wiring.
FIG. 3 illustrates another example of module division. In this division example, a semiconductor integrated circuit 40 is divided into two modules 41 through 42. In FIG. 3 too, the module is described as a “BLOCK”. A solid line separating the module 41 from the module 42 indicates a boundary.
In the module 41, cells are disposed in positions fairly away from a boundary with the module 42. In the module 41, similarly cells are also disposed in positions fairly away from a boundary with the module 42. Thus, a distance between adjacent cells CL is increased in a direction orthogonal to the boundary in a shape of pinching the boundary. This is because space between cells is made a buffer area in which the wiring and the like of one module are not affected by another module.
By working out a floor plan, it can be checked whether all functions can be realized in a desired chip area. If a useless area seems to occurs, the useless area can be deleted. Thus, conventionally, in working out a floor plan, the minimization of the chip area is focused. This is because by minimizing the chip area, the number of chips collected from one semiconductor wafer can be increased and its productivity can be improved.
However, the fineness of a semiconductor integrated circuit by the progress of a process technology and the increase of a circuit scale accompanying the fineness greatly is affecting the execution of a detailed design for determining the disposition of cells and wiring. More particularly, the increase of the circuit scale is making a process time needed to execute a detailed design longer. The fineness of a process makes optimal wiring more difficult. In order to perform an optimal wiring, it is preferable to more appropriately determine the disposition of a module terminal. Therefore, it is considered that in the pre-stage of a detailed design, a design might be made taking the detailed design into consideration more.
As technical reference literature, there are Japanese Laid-open Patent Publication Nos. H8-44784, 2003-30266 and 2002-215704.